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As VLSI technology scales to deep sub-micron, design for interconnections becomes increasingly challenging. The traditional bus routing follows a sequential bit-by-bit order, and few works explicitly target inter-bit regularity for signal groups via multi-layer topology selection. To overcome these limitations, we present Streak, an efficient framework that combines topology generation and wire synthesis...
The curvature effect of the 3-D layout may result in a severe deterioration of the breakdown voltage in a power lateral double-diffused MOS (LDMOS). In this paper, a novel 3-D analytical model is proposed to provide the physical insight of curvature effect in small radius region by solving the 3-D Poisson in cylindrical coordinates. The proposed model indicates that the curvature effect equivalently...
Dummy fill insertion is widely applied to significantly improve the planarity of topographic patterns for chemical mechanical polishing process in VLSI manufacture. However, these dummies will lead to additional parasitic capacitance and deteriorate the circuit performance. The main challenge of dummy filling algorithms is how to balance multiple objectives, such as fill amount, density variation,...
In this paper, we discuss emerging nanolithography technologies including double/multiple patterning, extreme ultra-violet lithography, electron-beam lithography, and their interactions with VLSI CAD. These technologies all have different manufacturing processes with their own challenges/issues. Meanwhile, nanometer VLSI designs and mask synthesis have to be co-optimized with these process technologies...
The semiconductor industry is facing a critical research challenge: design future high performance and energy efficient systems while satisfying historical standards for reliability and lower costs. The primary cause of this challenge is device and circuit parameter variability, which results from the manufacturing process and system operation. As technology scales, the adverse impact of these variations...
Design rule has been a primary metric to link design and technology, and is likely to be considered as IC manufacturer's role for the generation due to the empirical and unsystematic in nature. Disruptive and radical changes in terms of layout style, lithography and device in the next decade require the design rule evaluation in early development stage. In this paper, we explore VLSI CAD researches...
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