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Based on the requirement of IPD RF SIP application, the silicon based inductor and capacitor and rules have been studied at first. Meanwhile, a two-order silicon-based 2.4GHz bandpass filter with the size of 1.8mm*1.8mm was obtained by the combination of inductances and capacitors. The insertion loss at 2.4GHz is −1.35dB. Furthermore, to improve the selective of the bandpass filter, one transmission...
This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the...
This paper presents a frequency-shaping (FS) neural recorder with automatic bandwidth adjustment. The proposed recorder inherently attenuates electrode offset and motion artifacts, compresses neural data dynamic range by 4.5-bit, and achieves a 3 pF input impedance to better support chronic recording experiments. A major drawback of an FS recorder is larger input referred noise due to noise aliasing...
In this paper, a CMOS LC-VCO with low phase noise for UHF RFID reader is proposed. A symmetrical second-harmonic resonant filtering technology is adopted to suppress the phase noise. The proposed LC-VCO is designed in Jazz 0.18 μm SiGe BiCMOS technology. The post-simulation results show that in the whole tuning range of 1.45 GHz to 2.02 GHz, the designed VCO has an excellent phase noise of lower than...
This paper presents a frequency-shaping (FS) neural recording architecture and its implementation in a 0.13 m CMOS process. Compared with its conventional counterpart, the proposed architecture inherently rejects electrode offset, increases input impedance 5–10 fold, compresses neural data dynamic range (DR) by 4.5-bit, simultaneously records local field potentials (LFPs) and extracellular spikes,...
This paper presents a frequency-shaping (FS) neural recording interface that can inherently reject electrode offset, 5-10 times increase input impedance, 4.5-bit extend system dynamic range (DR), and provide much more tolerance to motion artifacts and 50/60 Hz power noise interferences. It is supposed to be more suitable for long-term brain-machine-interface (BMI) experiments. To achieve the mentioned...
Several power and area efficient multi-bit quantizers are discussed in this paper. Through the comparison and analysis of the reported quantizers, a novel ultra-low power MOSFET-only micromation one for implantable neural applications is proposed to optimize the area and power consumption with the use of high density MOSCAP and dynamic comparators. Simulated in a 0.18 μm 1P6M CMOS process, the density...
A 9μW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35μm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance,...
Two-stage Class-A switched-opamp (SO) is the most popular module in previous low voltage low power SO sigma-delta modulators (SDM). The SO saves about 30%~40% of the total power since its output stage is just turned off at the integrating phase. To further increase efficiency a novel high power efficiency class AB current mirror SO is proposed in this paper. By turning off the entire SO together with...
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