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We first-time demonstrate gray-scale control by pulse-width modulation for silicon thermo-optic (TO) phase shifters using monolithic MOSFET. This work enables simple and power efficient control of TO modules without using DAC and analog current drivers.
We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation,...
An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive...
Dual channel CMOS composed of InGaAs n- and Ge p-MOSFETs is considered to be an ultimate CMOS structure because high mobility of both electron and hole can be obtained [1]. Although the fabrication and independent transistor operations of InGaAs n- and Ge p-MOSFETs on the same wafer with common gate stacks (2D integration) have been demonstrated [2], the InGaAs/Ge functional CMOS has not been demonstrated...
We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (Wfin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that Wfin scaling effectively improved cut-off properties at Nd up to 5 × 1018 cm−3 and the electron mobility in the narrowest channel (Wfin =...
We fabricated gated 40,000-tip HfN-FEAs and evaluated HfN-FEA as an active device. The vacuum transistor has triode structure of a gated HfN-FEA and collector electrode. This vacuum transistor has collector current of 1.1 mA, transconductance of 0.27 mS, collector resistance of 2.8 MΩ and voltage amplification factor of 750 when applying emitter voltage of 58 V. This vacuum transistor amplified ac...
High-k/Ge with strontium germanide interlayer has been applied for both p- and n-MISFETs. The observed Jg-EOT trend in the Ge-MISCAPs exhibits comparable or superior leakage characteristics to that of state-of-the-art HfSiON gate dielectrics on Si down to an EOT of 0.96nm. The drive current of the p-MISFETs increases with the EOT scaling around 1nm without μeff degradation. Furthermore, reasonable...
Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The...
We have successfully suppressed threshold voltage variations due to pattern effect problems and random dopant fluctuation (RDF) using an integrated FSP-FLA technology. The serious problem of the pattern effect in FLA can be solved by using a light-absorber carbon film process, together with FSP-FLA. We estimated the temperature range in our test chip was within 10°C, being the same level obtained...
We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull ?? values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained...
We have succeeded in suppressing random threshold voltage (Vth) fluctuations by controlling capping-layers and high-k materials with metal gate first stacks for 22 nm-node devices. By employing 1-2 mono Y2O3-layers on HfSiON films, Vth fluctuations are the same as with non-capped samples, while maintaining excellent Vth controllability (|??Vth| > 180 mV). Furthermore, the devices exhibit high device...
A field emitter array (FEA) is expected for operation under a server environment. We focused on hafnium nitride (HfN) for the cold cathode metal, because it possesses relative lower work function [1] and high resistance against oxidation at high temperature [2]. We have already reported fabrication of HfN-FEA and emission properties of HfN-FEA at high temperature [3], but we have not examined HfN-FEA...
We have presented functional annealing data using the FSP-FLA (flexibly-shaped-pulse flash lamp annealing), together with some examples of the multi-functionality. First, we showed that the FSP-FLA can control thermal budget whilst sustaining high dopant activation, recovering crystalline defects, and controlling thermal diffusion length. Secondly, by combining impulses from conventional FLA and the...
We propose the suitable FLA method for pFET device activation by using flexibly-shaped-pulse FLA (FSP-FLA). For the activation annealing by FLA on B without pre-amorphous implantation (PAI) process, increase in preheat temperature before flash is the most effective. By using FSP-FLA, ~1000degC 10-ms preheat was performed. It achieves very shallow and high activated junction without PAI equivalently...
We demonstrated for the first time the device performance of (110) nMOSFETs featuring a Si migration process, resulting in better mobility and modified shape of the narrow active region, and ultra-shallow Al implantation after nickel silicide (NiSi) formation, resulting in reduced parasitic resistance. We found that these processes made the performance of (110) nMOSFETs competitive with that of (001)...
High-performance planar, bulk CMOS technology for 45nm nodes and beyond is reviewed from the point of mobility enhancement techniques and millisecond annealing techniques. Through continuous efforts to increase on-current with the strained techniques while scaling transistor dimensions with millisecond annealing, competitive high-end CMOS technology for 45nm node was realized.
We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance...
We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and...
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