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In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe...
For the anti-ESD reliability consideration, the drain-side with super-junction structures and “npn” embedded type SCRs of nLDMOS transistors are investigated in this paper. From the experimental data, we can find that the layout manner of super-junction types in the drain-side have positive impacts on the anti-ESD capability. On the other hand, as the drain-side added another item i.e. an embedded...
Repercussions on the reliability capability and electrical performance of power p-channel LDMOS devices by different discrete-distributed architectures in the drainside are investigated in this paper. Here, in order to effectively improve the reliability issues, a drain-side "NPN" and "PNP" styles of pLDMOS-SCR with some discrete-distributed areas arrangement are fabricated by...
For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its It2 value is improved by using this manner...
The impact of scaling in advanced RF/MS-CMOS has been extensively discussed but there has not been a publication that compares the RF characteristics of 28nm high-K metal gate HKMG and PolySiON technologies fabricated in the same facility. In this work, we show that HKMG improves transistor fT and increases varactor tunning range. However, it can actually decrease fmax. We examine how process features...
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