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A 10-bit single-channel SAR ADC is designed in a 130nm CMOS technology. An original DAC is proposed, merging a binary-weighted structure and a C/2C topology in order to reduce overall energy consumption. A built-in calibration circuit improves the conversion accuracy. The proposed SAR ADC samples at 6.66MHz, achieving a SNDR of 49.78 dB for a 1MHz input signal (ENOB of 8 bits). The simulated INL is...
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