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On-chip linear decompression-based schemes have been widely adopted by industrial circuits nowadays to effectively reduce the ever increasing test data volume and test time. Though they can easily achieve relatively high compression ratio, there is a bound of effective compression ratio for these compression schemes. Prior work tried to address this problem by trying different compression architectures...
A high-resolution all-digital duty-cycle corrector (ADDCC) with a novel pulse-width detector in cell-based design is presented. This work provides a wider acceptable duty-cycle range from 10% to 90% and a larger operation frequency range from 100MHz to 3.6GHz. We rely on an “Exponentially Segmented Binary Search” method for increasing the locking speed. Based on three types of...
Extraordinary power consumption during the scan test may inadvertently cause a functional good die to fail. This paper proposes a peak power reduction algorithm for the scan test which considers both the shift cycles and capture cycles simultaneously to limit the peak power of all test cycles during the test generation. In addition, the analysis also recommends the types of circuit structures that...
In this poster, we share our industrial experiences on running chain diagnosis and PFA (Physical Failure Analysis) on a wafer that suffered from low yield. In addition, case study on PFA will be illustrated.
Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation...
In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis...
In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited...
We introduce in this paper a new scan test methodology that can be programmed to execute in one of two gears - that is, the low-shifting-power scan, and the low-capture-power scan, in one single scan-architecture. This two-gear method provides layered treatment to potential power-induced test failure. First, it attempts to perform scan test in gear 1 without any test time overhead over the traditional...
Scan is a widely used Design-for-Testability technique to improve test and diagnosis quality. Many defects may cause scan chains to fail. In this paper, an observation point oriented Deterministic Diagnostic Pattern Generation (DDPG) method was proposed for compound defects, which tolerates the system defects during scan chain diagnosis. Instead of sensitizing multiple paths proposed in our prior...
In this paper, we study the impact, detection and diagnosis of the defect inside a scan cell, which is called scan cell internal defect. We first use SPICE simulation to understand how a scan cell internal defect impacts the operation of a single scan cell. To study the detectability and diagnosability of a scan cell internal defect in a production test environment, we inject scan cell internal defects...
In this paper, we present a test generation algorithm to improve scan chain failure diagnosis resolution. The proposed test generation algorithm creates a complete test set that guarantees each defective scan cell has unique failing behavior. This algorithm handles stuck-at fault and timing fault models. Problems and solutions that may happen in practical usage are discussed. We further extend the...
Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry. This Built-in Speed Grading (BISG) methodology uses an All-Digital Phase-Locked Loop (ADPLL) as the programmable clock generator to provide various clock...
In this brief, we present a robust new paradigm for diagnosing a scan chain with multiple faults that could have different fault types. As compared to previous methods, the major advantage of ours is the ability to not only target mixed multiple types of timing faults in the same scan chain but also tolerate non-ideal conditions, e.g., when these faults only manifest themselves intermittently. Unlike...
We address in this paper the defect modeling and testing of intra-cell bridging defects from the layout perspective. For defect modeling, we incorporate a butterfly structure to resolve the potential non-logical effect a bridging defect may cause. By doing so, a realistic Boolean fault model at the gate level can thus be generated for each defect under consideration. Furthermore, the test vectors...
Test cost is becoming a more and more significant portion of the cost structure in advanced semiconductor products. To address this issue, we propose HOY - a novel wireless test system with enhanced embedded test features. We present the concept, architecture, and test flow for future semiconductor products tested by HOY. Necessary technologies for the success of HOY also are presented, though most...
Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis...
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