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In this paper we discuss the end-to-end schedulability analysis for the bi-directional multistage pipeline systems, in which the arriving tasks could traverse the pipeline nodes in either of the two opposite directions. By accounting for the task execution overlap among nodes, we could derive an end-to-end delay bound formula for each task, which transforms the schedulability analysis of the task...
A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second...
A 5Gb/s signaling system was designed and fabricated in TSMC's 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution...
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