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Sub-30 nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30 nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated...
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal...
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