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FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF...
This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of...
The unique tail bits retention failure behavior is observed in the RRAM array. Unlike the previous reports on single device or the average value''s retention behavior, quick retention loss of tail bits is found for both LRS and HRS. By statistically characterized such relaxation effect of tail bits, physical models are built to quantitatively describe the relaxation behaviors of LRS and HRS. The correlation...
A central challenge for the complex network analysis is how to identify key nodes. Although there are many evaluation methods, most of them use single-criteria (degree or shortest path), which is often confronted with the problem of incomplete information on the structure of the complex network. Different criteria often lead to significantly different results. Therefore, this paper proposes a multi-criteria...
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