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Junction engineering solutions are presented in this work to improve the triggering and performance of SCR devices in an advanced 22nm SOI CMOS technology. Several SCR cathode junction formations are investigated including implants energy, dosage, with or without halo/extension implants. TLP and HBM results are presented in details.
We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
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