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We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.
Many types of ESD protection devices such as diodes, NFETs, SCRs and RC-triggered power clamps having different failure mechanisms are used in advanced CMOS technologies. Circuit schematic analysis and SEM failure analysis are utilized to clearly predict and identify the failing I/O driver/receiver devices and/or the various ESD protection devices during an ESD event.
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