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In this paper, electrical characteristic of TSV (Through Silicon Via) is analyzed. Firstly, equivalent circuit model of TSV is summarized. Modeling and electrical analysis of TSV is conducted, in which TSVs with ideal and non-ideal profiles are compared. And then, multi-TSV configuration in silicon interposer is modeled and analyzed. Capacitive and inductive coupling between TSVs are simulated. With...
Three-dimensional (3D) die stacking based on the Through Silicon Via (TSV) is a promising new packaging technology for its high performance, multi functionality, relatively smaller chip size and lower cost etc. However, the application of TSV in 3D SiP will introduce lots of new problems regarding the reliability, such as thermal stress, deformation, fatigue failure In this study, the thermal-mechanical...
In this paper, the potential application of combining cylindrical TSV and annular TSV into 3D integration was studied. First, the schematic fabrication process of cylindrical and annular TSV was proposed. Lumped equivalent circuit model of these different kinds of TSV structures from the physical configuration were studied and verified. Besides, 3D full wave electromagnetic (EM) simulations of cylindrical...
TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication...
As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip area, Through silicon via (TSV) is introduced to replace the large number of long interconnects needed in previous 2D structure. However, the thermal-mechanical reliability problems of TSVs, such as interfacial delamination, via cracking and so on, have become a serious reliability concern. In this paper,...
This paper considers metric 3D reconstruction with hierarchical merging. We first describe pairwise matching of images for spanning tree construction. The epipolar constraint is imposed on two related vertices. We then present a partition method to group the images into duplets or triplets for partial reconstruction. A robust hierarchical scheme that merges partial reconstruction together is used...
3D data representation becomes more popular, but the enormous points make the model reconstruction and the object recognition difficult. A simplification algorithm for 3D point cloud data integrating both the feature parameter and uniform spherical sampling is presented. At first, we define a feature parameter which includes the average distance parameter and the normal included angle parameter between...
This paper presents a robust and accurate self-calibration approach from unordered wide-baseline images. An optimization model based on affine transformation is introduced into propagation to acquire higher accuracy of quasi-dense correspondences. Our self-calibration algorithm is completed through two-layer iteration. In the inner layer, global objective function and local photometric consistency...
The ability to have applications draw computing power from a global resource pool to achieve high performance has become a new challenge for grid computing and Internet technologies. This challenge not only involves solving technical difficulties in the construction of Grid environments, it also involves resource sharing and advances grid system performance. This paper presents a RPMS (resource performance...
Active appearance model (AAM) has been widely used in face tracking and recognition. However, accuracy and efficiency are always two main challenges with the AAM search. The paper therefore proposed a fast appearance-model based 3D face tracking algorithm to track a face appearance with significant translation, rotation, and scaling activities by using stochastic meta-descent (SMD) optimization scheme...
We present a novel method to realize 3D adiabatically Spot-Size Converter (SSC) structures by standard silicon micromachining technics, for efficient coupling from single-mode fiber or free-space to silicon photonic chip. The SSC is comprised of I/O waveguides and a 3D tapered coupler on silicon-on-insulator (SOI) substrate. The dimensions are decreased linearly in both vertical and horizontal directions...
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