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For the miniaturization of two-dimensional autocollimator, a method of using embedded measurement system instead of special host computer is presented. This system integrates CMOS image sensor's driving circuit, frame processing, adaptive exposure control, centroid subdivision and localization of cross, misalignment angle calculation, display driver and other functions within a FPGA chip, and the...
From the space and time dimension, the FPGA circuit is devised some levels with “computing unit + memory/register” via analyzing the characteristics of the FPGA circuit. Combined with the location importance, the connection degree among the nodes and their own soft error probability, an importance analysis model is proposed. And then the testing points are optimized based on the importance of each...
For the effect of signal propagation in the programmable logic device caused by single event effects (SEE) of the space environment, a method for assessing soft error rate based on the resource configuration of netlist-level circuit topology by SEE is proposed in this paper. This method makes use of the mapping relationship between the synthesized netlist and the device resource. Then the construction...
Programmable logic device FPGA has characteristics of flexible design, high efficiency design, short development cycle and low cost. The power of FPGA is divided into static power and dynamic power. The static power is mainly decided by the temperature, it is easy to get power by building a simple model. But the dynamic power is decided by many kinds of design resources. This article focuses on XC4VSX55...
A novel topology based on pentacle is proposed for network on chip (NoC). Johnson coding and global asynchronous local synchronous (GALS) are applied to improve the performance of NoC and the resource utilization of FPGA. Simulation results show that, compared with 2D Mesh and Octagon, Pentacle achieves average latency reductions of 30.7% and 15.0%, and increases throughput of 17.6% and 8.1%, respectively...
Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general...
HyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced. This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is a popular bus protocol in SOC architectures. Furthermore, this HyperTransport interface provides dedicated hardware support for cache coherence protocol...
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