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Two low-power, high-performance and low-clock-swing D Flip-Flops (DFFs), LN_TC_SA and LP_TC_SA, are proposed in this paper. These DFFs are extensively applicable as they utilize generic CMOS technology and need no additional power supply specially for the low clock swing sub-circuit by using two kinds of improved inverter designs. Simulation results show that the average leakage power and power delay...
A low power, low clock swing D flip-flop (DFF) based on C2MOS (Clocked CMOS) and sense amplifier (SA) is proposed in this paper. This DFF is extensively applicable as it utilizes generic CMOS technology and needs no additional power supply specially for the clock sub-circuit. Simulation result shows that the average leakage power and dynamic power of this DFF are reduced by 78.73% and 8.74% respectively,...
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