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We report a novel device which exploits the internally combined quantum mechanical Band-To-Band and Barrier Tunneling mechanisms to achieve improved performances and overcome the intrinsic low current drive limitations of conventional Tunnel FETs and the 60 mV/decade limitation of MOSFETs at room temperature. The new structure, including an ultra-thin dielectric between metal source and silicon channel,...
In this paper, general analytical models for threshold voltage Vt and subthreshold slope S of single gate (SG), symmetric double gate (DG) and ground plane (GP) MOSFETs are proposed. The effect of channel strain on Vt?? S and drain induced barrier lowering (DIBL) is also investigated. The proposed model has been employed to calculate Vt?? S and DIBL for various MOS structures. Additionally simulation...
Uniaxial stress induced by recessed or embedded Si1-yCy source/ drain in nanoscale nMOSFETs is computed using finite element method adopted in numerical process simulator. The lateral, vertical and perpendicular stress components Sxx, Syy and Szz, respectively, are determined as a function of mole fraction y in the range 0.5 - 2.5 % and channel length L between 22-130 nm. Simulation results show that...
In this paper, analytical models for threshold voltage Vt and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting Vt and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate Vt, S and drain induced barrier...
The influence of strain on the gate leakage current has been investigated analytically in detail for strained-Si channel MOSFETs for a range of gate voltages and the gate insulator thicknesses. Our analysis relies on the determination of surface potential by solving the Poisson's equation using both the analytical and numerical approaches. The analytical model for the gate leakage current density...
We have investigated the influence of gate bias voltage, applied to one of the two gates of the dual gate (DG) MOSFET, on the threshold voltage for different geometric dimensions, gate materials and drain to source voltage. In our studies we have employed the 2-D numerical device simulator ATLAS to determine the threshold voltage pertaining to DG MOSFETs. It is observed that the gate bias plays an...
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