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This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory...
This paper presents a dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. Each phase scans nonzero sub-matrices two by two in block row-wise order, and two phases are fully overlapped. It reduces memory accesses by 24.3-48.8%, and takes only 48-54 clock cycles per iteration. It is fabricated in SMIC 0.13 μm 1P8M CMOS process, which occupies 4.84 mm2, attains 847-955 Mb/s, and consumes...
In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS...
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