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This paper presents a dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. Each phase scans nonzero sub-matrices two by two in block row-wise order, and two phases are fully overlapped. It reduces memory accesses by 24.3-48.8%, and takes only 48-54 clock cycles per iteration. It is fabricated in SMIC 0.13 μm 1P8M CMOS process, which occupies 4.84 mm2, attains 847-955 Mb/s, and consumes...
In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS...
Based on the min-sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13 ??m standard CMOS process, the LDPC decoder has an estimation area of 14 mm2, a throughput of 135 Mbps with a frequency...
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