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This paper presents a programmable input/output interface circuit for some types of field programmable gate array (FPGA) devices which may be used in relatively high voltage (e.g. 5.5V) environments. The proposed circuit provides five different operation modes so that these FPGA devices are capable of connecting with multiple types of IC devices, including high voltage devices and PCI devices. In...
This paper presents a novel input/output interface circuit for field programmable gate array (FPGA) devices, which has high voltage tolerant and PCI compliant capabilities. In the proposed circuit, dynamic gate and N-well bias technology is used to eliminate gate-oxide overstress and Pad to output supply (Vcco) leakage current when FPGA devices operate with high voltage input, and to ensure that over-voltage...
This paper has investigated present radiation hardened FPGA manufacturers and SEU hardened method of configurable SRAM (CSRAM) applied to FPGA. A novel high-density single-event upset hardened CSRAM applied to BQV 300 FPGA is proposed, and this paper uses the mix-mode radiation hardened verification method to simulate the SEU hardened CSRAM. The proposed SEU-hardened CSRAM applied to FPGAs is SEU...
Field programmable gate arrays (FPGAs) is becoming one of the most widely used electronics devices. Because of its unique architecture, power estimation is a complicated task for FPGAs. This paper presents a novel power estimation framework for SRAM-based FPGAs. Considering both dynamic power and static power, a gate-level power model for configuration logic blocks (CLBs) and a transistor-level power...
A novel configurable no dead-zone digital phase detector is proposed in this paper. As an embedded SRAM is employed to store configuration data, detection sensitivity of the phase detector can be controlled by the configuration data according to different input frequency. Besides, the novel phase detector avoid dead-zone by adopting two flip-flops and generating three state during operation. The circuit...
A novel configurable frequency synthesizer based on delay-locked-loop (DLL) is presented in this paper, with maximum multiplication factor 10 and maximum division factor 16. A SRAM is employed to store configuration data for different multiplication and division factor. Users only need to change the data stored in the embedded SRAM to obtain frequency needed. The output frequency range is from 25...
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