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Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5 nm conformal shallow junctions at low energy with no silicon structure damage. N-type PH3 plasma-assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma-assisted doping at high wafer temperature showed no structure damage even at a...
An ultra-thinning down to 4-µm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-µm was approximately...
In this letter, we investigate the electrical behavior of vacancy defects in Ge at various thermal annealing conditions through electrochemical capacitance–voltage analysis. Then, the effects of the annealing process on Ge junction diodes were also studied with , transmission electron microscopy, and secondary ion mass spectroscopy measurements in the aspects...
200 mm and 300 mm device wafers were successfully thinned down to less than 10 μm. A 200 nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50 nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9 μm, switching charge showed no change by the...
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the...
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