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The Effect of silicon window polarity on partial-SOI (partial silicon-on-insulator, PSOI) LDMOS power devices under high-voltage operation is studied. Different polarities of the silicon window in PSOI LDMOSFETs are analyzed to investigate their effects on electrical characteristics: breakdown voltage (BV) and on-resistance (Ron). In partial-SOI LDMOSFETs, the P-type silicon window is considered as...
A novel lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a buried N-type layer (BNL) in partial silicon-on-insulator (PSOI) is introduced to achieve breakdown voltage (BV) above 600 V and reduce on-resistance . The BNL induces enhanced voltage into the buried oxide layer, which results in higher BV. The higher doping concentration in the BNL can provide...
The optical device of multi-touch based on an algorithm matrix and patterned design was investigated. The algorithm matrix for array scanning is derived using voltage divider rule with two configurations of equivalent circuits. The virtual high and low impedances are used for patterned design. The microelectromechanical systems technologies are carried out for fabrication process of multi-touch panel...
This paper performed a detail study on the strained PMOS fabricated on the (110) Si substrate. We showed that in the (110) plane, the four-fold symmetry direction, <111'>, has the ideal band-structure features for the uniaxial-process-induced hole mobility enhancement. We then characterized the mobility and back scattering ratio of the (110)/<111'> PMOS with multiple process induced stressors.
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