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Library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we first propose a modified Y3 LEAP cell that was originally invented by K. Yano, Y. Sasaki, K. Rikino and K. Seki. Secondly we propose a new technology dependent mapping technique and compare the results with...
Efficient technology mapping has become an important vehicle in deep-submicron technologies for improving performance-oriented synthesis. On the other hand, library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we propose three new library cells based on differential...
As the fabrication process technology has moved from submicron to deep submicron region, it has become essential to minimize the leakage power and the variability of the design parameters such as delay and leakage. Although dual-Vt approach has been proposed for runtime leakage power reduction significantly without compromise in performance, it suffers from the limitation of complex fabrication process...
As the fabrication process technology is moving from submicron region to deep submicron or nanometer region, the impact of process parameter variations are becoming more and more dominant, increasing the loss in yield due to variations in leakage power and delay. As a consequence, parametric yield loss has become a serious concern of the fabrication houses. This has opened up a challenge to the designers'...
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