The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A planar double-gate FD-SOI is compared with the bulk CMOS in terms of low-voltage operations. It turns out that due to the small VT variation the FD-SOI is suitable for deep-sub-1 V operations with improved voltage margin of RAM cells and sense amplifiers, and reduced speed variations of logic gates
Ultra-low voltage nano-scale embedded RAMs are described, focusing on RAM cells and peripheral circuits. First, challenges and trends of low-voltage RAM cells are discussed in terms of signal charge, signal voltage, and noise. ECC to cope with the ever-increasing soft-error rate, power-supply controls to widen the voltage margin of cells, and a fully-depleted SOI to reduce VT-variation are also investigated...
Low-voltage nanoscale embedded RAMs are described, focusing on RAM cells and peripheral circuits. First, challenges and trends of low-voltage RAM cells are discussed in terms of signal charge, signal voltage, and noise. ECC to cope with the ever-increasing soft-error rate, power-supply controls to widen the voltage margin of cells, and a fully-depleted SOI to reduce VT-variation are also investigated...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.