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A multi-capacitor coupled signaling structure is employed to enable low-power high frequency communications in 10 mm long interposer traces. On-chip Metal-Insulator-Metal (MIM) capacitor was used to implement the Multi capacitor structure. A continuous time feed forward tunable capacitive equalization was used to compensate for the frequency dependent losses. The multi-capacitor structure is used...
This paper compares the power efficiency of multiple 2D, 2.5D and 3D interconnect scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2(3) with POP, wide I/Os with through-silicon vias (TSVs) and interposers and 32 nm technology CMOS drivers with TSVs and on-chip wires. It was found that DDR3 with PCB is the lowest power efficiency (15.65 mW/Gbps) and custom designed CMOS drivers optimized...
A nested inductive connector, consisting of a single power channel and one or more data channels, is proposed as replacement for legacy conductive connectors in mobile devices. Advantages include minimized space in the mobile device, waterproofing, orientation independence, and resistance to stress through a breakaway mechanism. A simulation and analysis of relevant parameters, such as the transfer...
Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block...
The demand for high-density links is increasing as the trend towards more cost-effective and high-throughput systems continues. Whereas the conventional single-ended and differential signaling schemes need a guaranteed interpair spacing which imposes certain bounds on maximum achievable signaling density, multimode signaling can be utilized to further increase it. In this paper, first, the exacerbated...
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