The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper a high order temperature compensation current reference circuit was proposed, which is accomplished by two current source with opposite temperature coefficients (TC) to obtain a smaller TC. The proposed circuit with a simple structure designed in Global Foundries 0.18μm CMOS process, achieving a temperature coefficient of 30.7ppm/°C in the range of −50∼120°C, and the quiescent current...
This paper presents a capacitively-coupled chopper instrumentation amplifier (CCIA) for portable EEG detection devices. In this design, the current-reuse technology is adopted in the core amplifier and the ripple reduction loop (RRL) to cut down the power consumption of the whole system. A novel ripple reduction loop based on ping-pong auto-zeroing topology is proposed to reduce the ripple at the...
A low-power high-resolution Delta-Sigma modulator for audio codec, designed in Global-Foundries BCD 0.18µm 1P4M CMOS process, is presented. The modulator employs a fourth-order single-loop feedforward topology with a 3bit-quantizer. A novel structure of Switched-Opamp (SO) utilizing current-starvation and Slew-Rate (SR) boosting is adopted to meet the requirements of high performance and fast settling...
This paper presents a SAR ADC for biomedical application, which has a strict limit on its power consumption. Thus, two techniques are introduced into its design: a novel ladder-based reconfigurable time domain (RTD) comparator is proposed to reduce the noise and to adjust power according to inputs automatically; and a novel clock distribution circuit is utilized to save more than 55% power consumption...
A low power successive approximation register ADC (SAR ADC) using a high performance integer-based split capacitor array combining with a mixed switching strategy is presented in this work. The split capacitor is chosen to be 2 times unit capacitance rather than the traditional non-integer value which is difficult to get. This array features high linearity, low area and power consumption. Besides,...
Several power and area efficient multi-bit quantizers are discussed in this paper. Through the comparison and analysis of the reported quantizers, a novel ultra-low power MOSFET-only micromation one for implantable neural applications is proposed to optimize the area and power consumption with the use of high density MOSCAP and dynamic comparators. Simulated in a 0.18 μm 1P6M CMOS process, the density...
A 9μW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35μm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.