Search results for: YangYuan Wang

Items from 1 to 20 out of 153 results

chapter

Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator

Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, more

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) > 780 - 785

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented for the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found in FinFET silicon data of NBTI aging. Especially, instead of ignoring or less accurate NBTI recovery effect model in traditional...

chapter

New Insights into the Amplitude of Random Telegraph Noise in Nanoscale MOS Devices

Zexuan Zhang, Shaofeng Guo, Xiaobo Jiang, Runsheng Wang, more

2017 IEEE International Reliability Physics Symposium (IRPS) > 3C-3.1 - 3C-3.5

2017 IEEE International Reliability Physics Symposium (IRPS)

Amplitude distribution of random telegraph noise (RTN) in nanoscale CMOS technology is an open question, with both lognormal and exponential distributions widely reported in literatures. In this paper, we experimentally clarified the underlying reasons for the first time, and revealed that the trap coupling effect is the missing role behind the divergent measured results of RTN amplitude statistics...

article

A Novel Tunnel FET Design With Stacked Source Configuration for Average Subthreshold Swing Reduction

Chunlei Wu, Qianqian Huang, Yang Zhao, Jiaxin Wang, more

IEEE Transactions on Electron Devices > 2016 > 63 > 12 > 5072 - 5076

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band...

chapter

New approach for understanding “random device physics” from channel percolation perspectives: Statistical simulations, key factors and experimental results

Zhe Zhang, Zexuan Zhang, Runsheng Wang, Xiaobo Jiang, more

2016 IEEE International Electron Devices Meeting (IEDM) > 7.2.1 - 7.2.4

2016 IEEE International Electron Devices Meeting (IEDM)

The concept of percolative channel is essential for understanding statistical variability and reliability in nanoscale transistors. In this paper, the quantitative factors of channel current percolation path (PP) are comprehensively studied in planar and FinFET devices for the first time, with statistical simulations and experimental characterizations. The properly-defined PP parameters are well quantified...

chapter

Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

Qianqian Huang, Rundong Jia, Jiadi Zhu, Zhu Lv, more

2016 IEEE International Electron Devices Meeting (IEDM) > 31.5.1 - 31.5.4

2016 IEEE International Electron Devices Meeting (IEDM)

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of...

chapter

Localized metal doping effect on switching behaviors of TaO_x-based RRAM device

Zongwei Wang, Jian Kang, Yichen Fang, Zhizhen Yu, more

2016 16th Non-Volatile Memory Technology Symposium (NVMTS) > 1 - 3

2016 16th Non-Volatile Memory Technology Symposium (NVMTS)

Memory unit, especially the non-volatile memory (NVM), is an indispensable component in a high performance electronic systems which aims at efficient information processing and storage. Resistive random access memory (RRAM) is one of the most promising candidates among the emerging memory technologies. However, optimization of the variability introduced by the intrinsic stochastic nature of filament...

chapter

A low power self-turnoff program method for one-time programmable memory

Ling Shen, Yongan Zheng, Fan Yang, Huailin Liao, more

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) > 579 - 581

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown...

chapter

Resistive-gate field-effect transistor exhibiting steep subthreshold slope of 5mV/dec and high ION/IOFF ratio

Qianqian Huang, Zongwei Wang, Yue Pan, Yangyuan Wang, more

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) > 38 - 40

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

In this paper, a new steep-slope device concept of resistive-gate field-effect transistor (RG-FET), which is operated by electrically induced abrupt resistance change of gate stacks, is discussed in detail and experimentally optimized. The fabricated RG-FET demonstrates both an ultra-steep subthreshold slope of below 5mV/dec over almost 2 decades of drain current and a high on-current competitive...

article

Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior

Chunlei Wu, Ru Huang, Qianqian Huang, Jiaxin Wang, more

IEEE Electron Device Letters > 2016 > 37 > 1 > 20 - 23

In this letter, design guideline for complementary heterostructure tunnel FETs (C-HTFETs) is proposed based on the insight into the tradeoff between n-type and p-type HTFETs optimization. For the first time, the contradiction of source/channel material selection between n-type and p-type HTFETs is addressed, indicating that HTFETs integrated on the same materials system cannot achieve optimized n-type...

chapter

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Qianqian Huang, Rundong Jia, Cheng Chen, Hao Zhu, more

2015 IEEE International Electron Devices Meeting (IEDM) > 22.2.1 - 22.2.4

2015 IEEE International Electron Devices Meeting (IEDM)

We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration...

chapter

Multi-finger Schottky-Barrier tunneling FET with hybrid operation mechanism for steep transition and high on current

Ru Huang, Qianqian Huang, Chunlci Wu, Jiaxin Wang, more

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) > 61 - 62

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

This paper discusses a kind of novel steep-slope switch device, named as multi-finger Schottky-Barrier TFET (MFSB-TFET), with hybrid adaptive operation mechanism, for higher on current, steeper slope as well as low off current. With the on state dominated by Schottky injection current, transition region dominated by band-to-band tunneling and the off current greatly suppressed with increased effective...

article

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-<roman>nm</roman> CMOS

Yixiao Wang, Le Ye, Huailin Liao, Ru Huang, more

IEEE Transactions on Circuits and Systems II: Express Briefs > 2015 > 62 > 3 > 296 - 300

A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational...

chapter

Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

Qianqian Huang, Ru Huang, Chunlei Wu, Hao Zhu, more

2014 IEEE International Electron Devices Meeting > 13.3.1 - 13.3.4

2014 IEEE International Electron Devices Meeting (IEDM)

In this paper, a novel TFET design, called Pocket-mSTFET (PMS-TFET), is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from circuit design perspective, TFETs performance in terms of I_ON, I_OFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally...

chapter

DTMOS mode as an effective solution of RTN suppression for robust device/circuit co-design

Shaofeng Guo, Ru Huang, Peng Hao, Mulong Luo, more

2014 IEEE International Electron Devices Meeting > 12.6.1 - 12.6.4

2014 IEEE International Electron Devices Meeting (IEDM)

In this paper, using DTMOS as an effective solution of RTN suppression without device/circuit performance penalty is proposed and demonstrated for the first time, with experimental verification and circuit analysis. The experiments show that RTN amplitude is greatly reduced in DTMOS mode, which is even better than the body-biasing technique of FBB, due to the efficient dynamic modulation mechanism...

chapter

New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits

Jibin Zou, Runsheng Wang, Shaofeng Guo, Mulong Luo, more

2014 IEEE International Electron Devices Meeting > 34.5.1 - 34.5.4

2014 IEEE International Electron Devices Meeting (IEDM)

In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models are proposed, which successfully interpret...

chapter

Resistive switching in organic memory devices for flexible applications

Ru Huang, Yimao Cai, Yefan Liu, Wenliang Bai, more

2014 IEEE International Symposium on Circuits and Systems (ISCAS) > 838 - 841

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The organic resistance memories show great potentials for future flexible applications. In this paper the main challenges and typical recent progress of the organic resistance memory devices are discussed. A kind of single-component polymer resistance memory device based on polychloro-paraxylylene (parylene-C) is focused, with excellent chemical stability and high CMOS process compatibility as well...

chapter

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

Qianqian Huang, Ru Huang, Cheng Chen, Chunlei Wu, more

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers > 1 - 2

2014 IEEE Symposium on VLSI Technology

The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f² LFN dependence can be observed in large TFETs with large device to device variability,...

article

A 4.2 mm $^{2}$ 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS

Long Chen, Yixiao Wang, Chuan Wang, Jiayi Wang, more

IEEE Transactions on Circuits and Systems I: Regular Papers > 2014 > 61 > 1 > 280 - 292

This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5–3.5 dB at VHF band and 2–3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further...

article

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

Chunlei Wu, Ru Huang, Qianqian Huang, Chao Wang, more

IEEE Transactions on Electron Devices > 2014 > 61 > 8 > 2690 - 2696

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between...

article

Resistive-Gate Field-Effect Transistor: A Novel Steep-Slope Device Based on a Metal—Insulator—Metal—Oxide Gate Stack

Qianqian Huang, Ru Huang, Yue Pan, Shenghu Tan, more

IEEE Electron Device Letters > 2014 > 35 > 8 > 877 - 879

A novel silicon-based resistive-gate field-effect transistor (ReFET) with metal-insulator–metal-oxide gate stack is proposed. With the abrupt resistance change event from high-resistance state to low-resistance state in the introduced insulator layer, the threshold voltage of ReFET can be suddenly decreased, resulting in an abrupt switching of drain current. The device is capable of sub-60-mV/decade...

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SILICON (30)
MOSFET (25)
LOGIC GATES (24)
CMOS INTEGRATED CIRCUITS (18)
NANOWIRES (18)
SWITCHES (16)
MOSFETS (15)
RESISTANCE (14)
ELEMENTAL SEMICONDUCTORS (13)
CMOS TECHNOLOGY (12)
SI (11)
ELECTRODES (10)
PERFORMANCE EVALUATION (9)
NANOSCALE DEVICES (8)
TRANSISTORS (8)
CMOS PROCESS (7)
NONVOLATILE MEMORY (7)
RANDOM-ACCESS STORAGE (7)
SUBSTRATES (7)
TIN (7)
ANNEALING (6)
DEGRADATION (6)
FABRICATION (6)
MICROELECTRONICS (6)
RRAM (6)
SILICON-ON-INSULATOR (6)
THERMAL STABILITY (6)
CUTOFF FREQUENCY (5)
FLUCTUATIONS (5)
GAIN (5)
ION IMPLANTATION (5)
NOISE (5)
POLYMERS (5)
RADIO FREQUENCY (5)
STRESS (5)
CLOCKS (4)
CMOS DIGITAL INTEGRATED CIRCUITS (4)
COPPER (4)
DEVICE PHYSICS (4)
DIELECTRICS (4)
INTEGRATED CIRCUIT MODELING (4)
JUNCTIONS (4)
LOW-POWER ELECTRONICS (4)
NANOELECTRONICS (4)
NEGATIVE BIAS TEMPERATURE INSTABILITY (4)
SEMICONDUCTOR DEVICE MODELING (4)
SIMULATION (4)
SOI (4)
SURFACE POTENTIAL (4)
TEMPERATURE MEASUREMENT (4)
TUNNELING (4)
AGING (3)
ALGAN/GAN (3)
BALLISTIC TRANSPORT (3)
BORON (3)
CIRCUIT STABILITY (3)
CMOS (3)
CMOS BACK-END PROCESS (3)
COMPACT MODELING (3)
CONTACT RESISTANCE (3)
DELAY (3)
DESIGN OPTIMIZATION (3)
DIGITAL CIRCUITS (3)
ELECTRIC FIELDS (3)
ELECTRON TRAPS (3)
FLASH MEMORIES (3)
FLASH MEMORY (3)
GATED-DIODE (3)
GOLD (3)
HOT CARRIER INJECTION (3)
HOT CARRIERS (3)
LOW POWER (3)
MATERIALS (3)
METALS (3)
MODELING (3)
PARASITIC CAPACITANCE (3)
PARYLENE-C (3)
PHASE LOCKED LOOPS (3)
PHASE NOISE (3)
POISSON EQUATION (3)
R-G CURRENT (3)
RADIOFREQUENCY INTEGRATED CIRCUITS (3)
RANDOM ACCESS MEMORY (3)
RECEIVERS (3)
RELIABILITY (3)
RESISTIVE SWITCHING (3)
SCALING (3)
SELF-HEATING EFFECTS (3)
SEMICONDUCTOR DEVICE MODELS (3)
SHORT-CHANNEL EFFECTS (3)
SI:B (3)
SILICON NANOWIRE MOSFET (SNWT) (3)
SILICON NANOWIRE MOSFETS (SNWTS) (3)
SILICON NANOWIRE TRANSISTORS (3)
SIZE 0.18 MUM (3)
TEMPERATURE (3)
THRESHOLD VOLTAGE (3)
TITANIUM COMPOUNDS (3)
TUNGSTEN (3)
UHF INTEGRATED CIRCUITS (3)
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INFONA - science communication portal

Search results for: YangYuan Wang

Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator

New Insights into the Amplitude of Random Telegraph Noise in Nanoscale MOS Devices

A Novel Tunnel FET Design With Stacked Source Configuration for Average Subthreshold Swing Reduction

New approach for understanding “random device physics” from channel percolation perspectives: Statistical simulations, key factors and experimental results

Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

Localized metal doping effect on switching behaviors of TaO_x-based RRAM device

A low power self-turnoff program method for one-time programmable memory

Resistive-gate field-effect transistor exhibiting steep subthreshold slope of 5mV/dec and high ION/IOFF ratio

Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Multi-finger Schottky-Barrier tunneling FET with hybrid operation mechanism for steep transition and high on current

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-<roman>nm</roman> CMOS

Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

DTMOS mode as an effective solution of RTN suppression for robust device/circuit co-design

New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits

Resistive switching in organic memory devices for flexible applications

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

A 4.2 mm $^{2}$ 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

Resistive-Gate Field-Effect Transistor: A Novel Steep-Slope Device Based on a Metal—Insulator—Metal—Oxide Gate Stack

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