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Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal...
An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La2O3 stacking. Among silicates, La2O3/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold...
Advantage of La2O3 over HfO2 MOSFET has been experimentally examined. Silicate reaction especially observed at La2O3/Si interface has been found to suppress the formation of SiO2 layer to realize direct contact, which is useful for further scaling in equivalent oxide thickness (EOT). Due to the lack of interfacial layer, La2O3 has showed relatively high interfacial state density, however, the effective...
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