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In this paper we propose a high level test pattern generation scheme for integrated circuits designed at the behavioral level. The scheme is based on the directed symbolic execution that results a symbolic expression for a test path. A test pattern for a circuit under test is derived from actual values of input variables on evaluation of the resulting symbolic expression of a test path and ensures...
The size and complexity of the very large scale integrated circuits are ever increasing because of rapid advancements of deep-submicron and nanometer technologies. It has become imperative to address and attack the problems associated with verification at earlier design stages. The paper proposes a high level design verification scheme for the circuits designed at the behavioral level. The scheme...
This paper presents an efficient automatic test pattern generation paradigm to gain confidence in the correctness of designs of circuits. The paradigm is based on selection of a goal node determined by applying basic graph traversal on a graph model of a circuit under test and validation of a path passing through the goal node. The set of test patterns for the paths through a goal node suffices to...
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