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Two numerical simulation techniques are presented to investigate the heating issues in nanoscale Si devices. The first one is the Monte Carlo simulation for both electron and phonon transport, and the transient electrothermal analysis is carrier out in n+-n-n+ device with the n-layer length of 10 nm. The second is the molecular dynamics approach for simulating the atomic thermal vibration in the nanoscale...
Electron transport in bulk silicon with ordered dopant arrays is studied using an ensemble Monte Carlo (EMC) technique coupled with molecular dynamics (MD) method. This work is motivated by a recently developed single-ion implantation (SII) technique, which enables us to fabricate a semiconductor device with an ordered dopant array. We numerically estimate the carrier mobility in silicon with such...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
The electron mobility degradation for HfSiON MISFETs was investigated. We found that the degradation had two origins; one is Coulomb scattering caused by fixed charges in HfSiON films and the other is phonon scattering by interfacial thin oxynitrided (SiON) layer; and HfSiO-related remote phonon scattering is not dominant. The mobility degradation caused by the Coulomb scattering and SiON phonon scattering...
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was...
Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility...
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