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In this paper, tunnel FETs (TFET) with different gate dielectrics are studied. The effects of gate dielectric constant in the TFET are investigated with qualitative analysis and numerical simulations. The regulation of gate-channel coupling and the modulation of electric field at the tunnel junction both contribute to the carrier tunneling in TFETs. The dominant one is determined by the topology of...
A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation...
Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be...
The Effect of silicon window polarity on partial-SOI (partial silicon-on-insulator, PSOI) LDMOS power devices under high-voltage operation is studied. Different polarities of the silicon window in PSOI LDMOSFETs are analyzed to investigate their effects on electrical characteristics: breakdown voltage (BV) and on-resistance (Ron). In partial-SOI LDMOSFETs, the P-type silicon window is considered as...
In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes...
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