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In this paper, we propose a two-phase method to solve the problem of the network component insertion for 3D application-specific Network-on-Chip (NoC). A model based on genetic algorithm is conducted at the first phase, in order to obtain optimal insertion positions of routers and network interfaces with minimal total network interconnection power consumption. Then some routers are merged to further...
Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked...
The diminishing momentum of Dennard scaling leads to the ever increasing power density of integrated circuits, and a decreasing portion of transistors on a chip that can be switched on simultaneously—a problem recently discovered and known as dark silicon. There has been innovative work to address the “dark silicon” problem in the fields of power-efficient core and cache system. However, dark silicon...
As the number of processing elements increases in a single chip, the interconnect backbone becomes more and more stressed when serving frequent memory and cache accesses. Network-on-Chip (NoC) has emerged as a potential solution to provide a flexible and scalable interconnect in a planar platform. In the mean time, three-dimensional (3D) integration technology pushes circuit design beyond Moore's...
In this paper, we present a two-phase floorplanning approach based on genetic algorithm to arrange each IP core reasonably into a fixed-outline rectangle for Application-specific Network-on-Chip (NoC) design. Our algorithm consists of core clustering and cluster floorplanning. These steps are done to arrange IP cores with optimizing communication power consumption and chip area. Experimental results...
In this paper, we present a thermal-aware mapping algorithm based on genetic algorithm that automatically maps IP cores onto 3D Mesh Network-on-Chip (NoC) architecture, which mainly takes the temperature deviation into account. In order to verify the efficiency of the algorithm, we applied our algorithm on various multimedia benchmark applications, and evaluated the performance and temperature with...
This paper presents a low-power and small-size variable gain amplifier (VGA) which consumes only 1.1mW and occupies only 132um × 59um in 0.18-um CMOS technology. The proposed circuit is implemented by Gilbert cells and an exponential function circuit for the dB linearity of the gain voltage. The gain of the VGA can be varied linearly in dB from −10dB to 50dB with respect to a control voltage from...
In this paper a conformal antipodal Vivaldi antenna array on a cylindrical surface for ultra-wideband (UWB) applications is proposed. The cylindrical antenna is mounted on the surface of the cylindrical object. The conformal antenna has good characteristics after a optimization for the geometry parameters of antenna. Vivaldi antenna array with four antenna on cylindrical surface can be designed with...
A fifth-order Gm-C low-pass filter, which employs source degeneration linearization technique, used in analog frontend anti-aliasing is presented. This filter was simulated in the TSMC 0.18-µm CMOS process design kit (PDK) with 5-fF/µm2 MIM capacitors. This simulated filter features corner frequency of 20MHz, power consumption less than 4mW, supply voltage of 2V, THD of 1% at 260mVpp. The total area...
This paper presents an all CMOS decibel-linear Automatic Gain Control (AGC). This AGC achieves large dynamic range with low power consumption. By applying digital switches to change exponential approximation function, four dynamic ranges (62, 50, 33, 26 dB) are realized. This AGC is implemented in TSMC 0.18-µm CMOS RF process. Measurement results show that this AGC achieves 60 dB linear range with...
An ultra-wideband low cross-polarization printed log-periodic dipole antenna (LPDA) is systematically investigated. The properties of the proposed antenna have been Simulated and optimized with electromagnetic simulation software FEKO 6.2. The antenna possess the operating bandwidth from 0.8GHz to 7.2GHz with the return loss less than −10dB, the cross-polarization and side lobe level are less than...
A novel 0.5THz integrated antipodal curvilinearly tapered slot antenna(ACTSA) with circular polarization is introduced in this paper. The proposed antenna is fed by traditional waveguide and circular polarization is achieved by antipodal curvilinearly tapered slot structure. The antenna structure is well suitable designed by Micro-electromechanical systems (MEMS) technology. The proposed antenna is...
A double-layer 90° corrugated terahertz (THz) horn antenna based on MEMS (Micro-electromechanical System) technology is proposed. This antenna is designed at the frequency range of 400GHz–500GHz. Through adding expansion aperture and chokes to the traditional structure, good antenna performance can be obtained. From the simulated result it shows a impedance bandwidth of 400–500GHz with input return...
This paper presents a terahertz high-gain antenna which has a certain beam scanning capability and the antenna also has an offset Cassegrain reflector structure. Beam scanning method is analyzed by the theory of quasi-optics. Moreover, we elaborate critical analysis algorithm of the antenna. Simulation results show that, in the initial position, the gain of the antenna is 44.98dB, the half-power beam...
A Ka-band front end of fully polarized microwave radiometer is designed, which consists of ortho-mode transducer (OMT) and multimode horn (MMH). The front end is analyzed using the finite element method. The simulation results show it has a good performance. The two ports isolation of the front end is larger than 53dB, the gain of the front end is larger than 22.4dBi, the sidelobe level is less than...
To solve the problems of congestion and fault tolerance for global communication management in network on chip (NoC), a novel dynamic routing scheme base on network monitor called DyRS-NM, is proposed for NoC application. DyRS-NM has the ability to locate dynamic congested or faulty links to detour them based on the overall network status values collected by network monitor, and also can balance the...
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