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Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line comparison, CAM is power-hungry. Thus, robust, high-speed and low-power sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore,...
The paper presents a new match line sense amplifier for Content Addressable Memory. It successfully addresses the weaknesses of contemporary designs. Extensive simulation results using a 1 V/65 nm CMOS process from STMicroelectronics have verified that the proposed sense amplifier outperforms other five contemporary designs in terms of energy consumption, area requirement and robustness. This is achieved...
In this paper we analyzed the IR drop problem in large scale content addressable memory (CAM) and proposed a simple yet efficient gated power transistor technique. Each row of CAM cells is powered by two metal rails, one for the memory element and another one for the comparison transistors and the match lines. The latter rail is powered by a row-based transistor, which presents a physical “gate” to...
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