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Rebooting computing using in-memory architectures relies on the ability of emerging devices to execute a legacy software stack. In this paper, we present our approach of executing compute kernels written in a subset of the C programming language using flow-based computing on nanoscale memristor crossbars. Our approach also tests the correctness of the design using the parallel Xyces electronic simulation...
The drastic increase in the commodity computer and network performance for the last generation has a resultant of faster hardware and more sophisticated software. But, the supercomputers of the current generation are still incapable of solving the current problems in the field of science, engineering, and business. This problems arises as a single machine cannot facilitate the availability of various...
We introduce a new compact in-memory computing design for implementing 8-bit addition using eight vertically-stacked nanoscale crossbars of one-diode one-memristor 1D1M switches. Each crossbar in our design only has 5 rows and 4 columns. Hence, the design may be used to fabricate a compact 8-bit adder that meets the size constraint of 50nm χ 50nm χ 50nm imposed by the electrical component of the Feynman...
There has been a surge of interest in the effective storage and computation of data using nanoscale crossbars. In this paper, we present a new method for automating the design of fault-tolerant crossbars that can effectively compute Boolean formula. Our approach leverages recent advances in Satisfiability Modulo Theories (SMT) solving for quantified bit-vector formula (QBVF). We demonstrate that our...
We are quickly reaching an impasse to the number of transistors that can be squeezed onto a single chip. This has led to a scramble for new nanotechnologies and the subsequent emergence of new computing architectures capable of exploiting these nano-devices. The memristor is a promising More-than-Moore device because of its unique ability to store and manipulate data on the same device. In this paper,...
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