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This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully...
We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates...
A novel quasi-silicon-on-insulator (quasi-SOI) flash memory cell is proposed for the first time. By utilizing quasi-SOI structure, program/erase (P/E) performance improvement is achieved due to the enhancement of electric field in the injection region, compared with conventional cell structure. Moreover, the off-state current at large drain bias is greatly reduced by 2 orders of magnitude with the...
In this letter, a novel Flash memory cell structure using dual doping polysilicon (p-n-p) as the floating gate, which can improve the cell performance and reliability, is proposed. Except for an additional large-angle tilted implantation, the fabrication technology is essentially compatible with standard CMOS technology. Measured results show that the new Flash cell with p-n-p-type floating gate can...
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