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We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented...
We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented...
Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory...
In this work a concept for true random number generator from jitter in bang-bang ADPLLs within systems-on-chip is presented. For this purpose the phase-frequency detector (PFD) output of an existing ADPLL clock generator bit is directly used as entropy source with zero power and chip area overhead. The randomness properties of the PFD data stream are analyzed and a lightweight, fully synthesizable...
Data processing on a continuously growing amount of information and the increasing power restrictions have become an ubiquitous challenge in our world today. Besides parallel computing, a promising approach to improve the energy efficiency of current systems is to integrate specialized hardware. This paper presents a Tensilica RISC processor extended with an instruction set to accelerate basic database...
This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction...
This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT...
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