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In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of Line (BEOL) for the experimental thermal characterization of the inter-die thermal resistance of wafer-pairs fabricated by hybrid Cu/dielectric wafer-to-wafer bonding. The thermal test structures include heater elements and temperature sensors. The measurement data is combined...
3D integration technology using thin die and Through-Silicon-Via, TSV, connections affect transistor and circuit behavior through electrical, mechanical and thermal interactions. The roadmap for further 3D technology development should focus on minimizing these effects.
A compact model or thermal resistor network of a 72-pins polymer stud grid array (PSGA) assembly is presented. A general thermal network is simplified to a compact model with seven resistors. Secondly, the effect of the chip dimensions on the different thermal resistors is investigated. Thirdly, the compact models are synthesized in a response surface model (RSM). Any customer can then calculate the...
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