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In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of intrinsic...
In this paper, the stability/performance of the conventional SRAM cell architectures have been demonstrated using a novel hetero-junction double gate tunnel FET (H-DGTFET) device at 15 nm technology node. This device has improved ON-current (ION) because of the decrease in width of the depletion region due to a highly doped layer placed in the channel near the source-channel junction. It results in...
We present an analytical model of 3D potential distribution for surrounding-gate (SurG) gate-all-around (GAA) MOSFET. The model is based on solution of Laplace's and Poisson's equations, where isomorphic polynomial functions are used to describe the potential distribution. The short channel effects are precisely accounted for by introducing z dependent characteristic length. From this, the device...
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