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We report on a 1D linear array of GHz ultrasonic transducers as an ultrasonic impedance imager for fingerprint sensing. This device is based on an all solid state aluminum nitride (AlN) transducer array that eliminates the need for released membranes. Compared to lower frequency (10–50 MHz) ultrasonic sensors, our device uses GHz ultrasonic pulses, generated by driving AlN pixel transducers at resonance...
A hybrid Time to Digital Converter (TDC) — Bang Bang (BB) All Digital Phase Locked Loop (ADPLL) architecture is proposed to optimize power, area, lock time, and design complexity. The Hybrid ADPLL architecture utilizes a low resolution two synthesizable Time to Digital Converters to achieve fast lock time, and then switches to a Bang-Bang like architecture once it is in the locked state. Such hybrid...
In this paper we present 1–3 GHz frequency ultrasonic interrogation of surface ultrasonic impedances. The chipscale and CMOS integration of GHz transducers can enable surface identification imaging for many applications. We use aluminum nitride piezoelectric thin films driven at maximum amplitudes of 4-Vpp to launch and measure pulse packets. In this paper we first use the contrast in ultrasonic impedance...
Bang-Bang Phase Locked Loops (BB-PLLs) exhibit a nonlinear response that is dependent on the magnitude of the phase error. This paper presents a novel Digital Loop Filter (DLF) with coefficients that adapt to the relative magnitude of the phase error, and hence, enhances system linearity. An All-Digital BB-PLL (BB-ADPLL) that incorporates the proposed DLF is implemented using 32nm technology. AMS...
Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the magnitude of the phase error, and thus, exhibits hard nonlinearity. This paper presents a generic modeling methodology for digital BB-PLLs in the locked state using simple time domain analysis. The proposed model predicts the response of BB-PLL...
In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW...
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