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A passive delta-sigma ADC with a voltage-controlled-oscillator (VCO) quantizer is presented. By employing the VCO quantizer, a single-bit quantizer is replaced with a multi-bit quantizer while an extra order of noise-shaping was provided. The proposed architecture does not need very large capacitors as compared to the conventional passive delta-sigma ADC. Furthermore, it also does not require external...
Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the...
A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an Nth-order IADC. The implemented third-order IADC achieves a measured dynamic range of 99.8 dB and an SNDR of 91 dB for a maximum input 2.2 VPP and 250...
A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported. It uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold. It was realized in the IBM 90 nm CMOS technology. The fabricated 90nm CMOS prototype device, for a 1 Vpp differential input range, experimentally shows a 74dB SNDR up to...
This paper presents a new stage-sharing technique in a discrete-time (DT) 2–2 MASH delta-sigma ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2–2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators...
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