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H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for testing H.264-IME block, but the test time usually...
In this paper, we propose a novel test technique to achieve both acceptable number of test patterns (NTP) and hardware overhead (HO) by finding a balance between them. Novel bijective and scalable cells are proposed to apply the technique on ILA-based (Iterative-Logic-Array) architectures. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable...
A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table...
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