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In this paper, we propose two C-testable design-for-testability (DFT) architectures for coordinate rotation digital computer (CORDIC) design. The first design is achieved by using scalable cells. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between hardware overhead (HO) and number of test patterns...
In this paper, a novel test technique is proposed to achieve C-testable DFT designs for arithmetic circuits. Base on famous iterative-logic-array (ILA) test scheme, basic bijective cells (one-to-one mapped I/O function) for adder, subtracter, adder-subtractor and multiplier are proposed. In particular, these basic cells are always bijective for any word-length n. Thus the bijective cells can be easily...
H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for testing H.264-IME block, but the test time usually...
In this paper, we propose a novel test technique to achieve both acceptable number of test patterns (NTP) and hardware overhead (HO) by finding a balance between them. Novel bijective and scalable cells are proposed to apply the technique on ILA-based (Iterative-Logic-Array) architectures. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable...
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