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Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit...
Power 6H- and 4H-SiC DIMOS test structures have been fabricated using a new technology. P-well formation was optimised from simulation study and previous experiments on high-energy Al implantation. Reduction of Al presence at interface and reduced defect formation during implantation were the main objectives of this optimisation. Complementary surface implantation of boron was performed to adjust...
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