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An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The...
The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology...
This paper advocates a system-aided DRAM scaling strategy, where the rationale is to embrace, instead of striving to tackle, the difficulty of storage node aspect ratio (A/R) scaling. In current practice, scaling down of DRAM cell size must be strictly accompanied with proportional scaling up of storage node A/R, in order to maintain the storage node capacitance and hence error-free memory operation...
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