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Semiconductor companies have developed 2.5D IC integration technology, which applies a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform for interconnecting and integrating heterogeneous chips horizontally and vertically as a transition approach to 3D IC. The existing Cu TSVs might make the silicon interposers more fragile, due to structural non-homogeneity and weak interface...
For the high-power LED applications, TAV (Through-aluminum-nitride-via) substrate with a high thermal conductivity provides better heat dissipation. However, the high thermal expansion coefficient mismatch between the AlN (Aluminum nitride) and copper film may cause the failure, and thus affect the reliability of TAV substrate. The objective of this study is to evaluate the reliability of TAV substrate...
The mechanical strength of the thin dies especially with copper through-silicon via (Cu-TSV), has to be determined for ensuring good yield during manufacture handling and packaging. In this study, three test methods: a line-load on elastic-foundation (LoEF) test, a 3-point bending (3PB) test and a 4-point bending (4PB) test are used for the strength determination of Cu-TSV thin memory dies. The results...
This study aims to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3D integrated circuit packaging. Prior to the study, the saturated current changes (or related carrier mobility changes) of both n- and p-MOS transistors from the finite element simulations are validated with experimental data. After model...
This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO2 layer effect, zero-stress temperature, single and array vias, through...
As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes...
When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy)...
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