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The mechanical strength of the thin dies especially with copper through-silicon via (Cu-TSV), has to be determined for ensuring good yield during manufacture handling and packaging. In this study, three test methods: a line-load on elastic-foundation (LoEF) test, a 3-point bending (3PB) test and a 4-point bending (4PB) test are used for the strength determination of Cu-TSV thin memory dies. The results...
This study aims to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3D integrated circuit packaging. Prior to the study, the saturated current changes (or related carrier mobility changes) of both n- and p-MOS transistors from the finite element simulations are validated with experimental data. After model...
This study is to numerically and experimentally investigate the effect of via-middle Cu through silicon via (TSV) on the mobility change (or related saturated current change, or drive current change) of transistors in the DRAM chip for 3D integration and further determine the keep-out zone (KOZ) in terms of key parameters such as SiO2 layer effect, zero-stress temperature, single and array vias, through...
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