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Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling...
This paper shows for the first time, the influence of back gate bias (VB) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (ΩG-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with VB increment,...
We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive...
Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi)...
This paper presents an experimental comparison of the analog performance between a triple-gate FinFET fabricated on Bulk (BFF) and on Silicon-On-Insulator — SOI (SFF) substrates. This comparison was performed based on the drain current, subthreshold swing, transconductance, output conductance and finally the intrinsic voltage gain. For narrow fin width, the SFF presents better performance than BFF,...
This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (VB=VG) over the conventional one (VB=0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (VB=k×VG) and the inverse eDT mode (VG=k×VB) were also considered and compared to the other...
The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations...
SOI multiple-gate devices (MuGFETs) have shown to be promising choices to continue scaling. The devices show excellent gate control and thus reduced short-channel effects. Additionally, by using high-k dielectrics a gate leakage current reduction can be achieved. The incorporation of nitrogen into these high-k materials can improve their thermal stability, reduce the dopant penetration and allow further...
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