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A mismatch-tolerant current-mode Sigma Delta (ΣΔ) Digital to Analog Converter (DAC) is presented here. The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range even as the ΣΔ step size and range are kept small to minimize ΣΔ switching noise. Mismatch between DAC current elements...
A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of −40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought...
A slew-rate controlled, 800Mbps voltage mode differential transmitter is presented here. An add-on, capacitive charge transfer based scheme is used to control output rise/fall times. The transmitter, designed and fabricated in a 65nm CMOS technology, occupies an active area of 0.02mm2 and consumes 2.7mW. Of this, the add-on slew-rate control occupies an area of 0.0027mm2, and consumes 0.5mW.
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