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We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and...
We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput...
Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer...
Chip-to-wafer bonding is a promising technology for 3D integration due to high production yield using known good dies (KGDs). However, conventional chip-to-wafer 3D integration lowers production throughput because pick-and-place chip assembly is employed. To overcome the problem, we proposed a new chip-to-wafer 3D integration using self-assembly by which many KGDs can be simultaneously, rapidly, and...
We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously self-assembled to a carrier wafer named “reconfigured wafer”. High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions....
We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously...
We developed a new self-assembled die bonder to produce three-dimensionally integrated circuit (3D IC) using a multichip-to-wafer bonding method in batch. In the self-assembled multichip bonder, large number of known good dies (KGDs) can be simultaneously transferred to an LSI wafer on which hydrophilic bonding areas with liquid droplets are prepared. The many KGD can be aligned to the bonding areas...
We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum...
We proposed a new three-dimensional (3-D) super-chip integration technology using self-assembly technique. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5 ??m. We have...
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