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We explored the properties and performance of copper-based metallic nanoparticle paste (MNPs) for interconnects applications in 3D heterogeneous integration. A patterning method was developed to process micron sized sintered MNPs structures. This enables the fabrication of IC interconnect test structures to characterise specific resistivity sintered MNPs and the contact resistances of sintered MNP...
Vertically aligned carbon nanotube arrays (CNTs) are a nanoscale material that can be grown from the bottom up in a fast and controlled manner to form large microstructures. Combined with thin conformal coatings, we gain accurate control over the material properties of nano-porous CNT arrays. This paper deals with three topics involving nanoscale materials for microfabrication; (1) microfabrication...
In this paper we report a novel transfer-free graphene fabrication process, which does not damage the graphene layer. Uniform graphene layers on 4" silicon wafers were deposited by chemical vapor deposition using the CMOS compatible Mo catalyst. Removal of the Mo layer after graphene deposition results in a transfer-free and controlled placement of the graphene on the underlying SiO2. Moreover,...
G4 LED lamps have difficulties to reach high lumen output within the required small form factor. Current technology used in G4 LED lamps was at first reviewed by analysis of 7 current commercialized products. Theoretical limitation was calculated under different design strategy scenarios. Furthermore, a detailed analysis of driver systems were carried out under thermal infrared imager. It has been...
The increased electrical currents used to drive light emitting diode (LED) cause significant heat generation in the solid state lighting (SSL) system. As the temperature will directly affect the maximum light output, quality, reliability and the life time of the SSL system, thermal management is a key design aspect in terms of cost and performance. Particularly for consumer SSL system, natural convection...
The stress in deposited silicon dioxide and silicon nitride layers that are used in the fabrication of self-aligned bipolar transistor structures, is evaluated. The intrinsic and thermal stress of the layers is measured and these values are used in a finite element process simulator to calculate the pressure in the silicon around the emitter window during processing. Bipolar transistors are fabricated...
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