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As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (VCCmin) of the SoC because of...
This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but...
A thyristor-based memory cell technology provides SRAM-like performance at 2times to 3times the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13mum 9Mb SOI test chip has a 0.562mum2 cell with a cell-R/W time <2ns
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