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FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %µm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability...
For the first time, we have successfully fabricated the Vth controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the Vth of the FinFET on the ETBOX is flexibly tuned from low Vth to high Vth with keeping low sub-threshold slope.
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper...
This paper discusses a role of the oxygen vacancy in HfO2/ultra-thin (UT) interfacial layer (IL) SiO2 gate stacks, focusing on the VFB roll-off. The metal/top-SiO2/HfO2/UT IL-SiO2/Si gate stacks have been studied. It is found for the first time that the VFB roll-off is eliminated by inserting 1~2 nm top-SiO2 between metal gate and HfO2. This elimination of the VFB roll-off is explained by compensating...
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